Recently, as semiconductor manufacturing process technology develops rapidly, a semiconductor chip for high voltage using a bipolar CMOS DMOS (BCD) process becomes smaller and more highly integrated. An electrostatic discharge (ESD) phenomenon in such a semiconductor chip causes the breakdowns of integrated circuit (IC) internal devices and metal wires, as well as circuit malfunctions due to electrostatic that is generated when electronic components and products are manufactured or in use and instantaneously discharged. Therefore, the ESD phenomenon is a very important factor to consider in the field of IC design. An electrical level of an ESD pulse applied to such a chip is very high, such as several kilovolts or several amperes, so that a device destruction phenomenon due to ESD can be very serious.
The requirement of an ESD immunity level is increased from 2 kV to 4 kV or 8 kV based on a human body model (HBM). As a result, an ESD phenomenon is one of the main factors that destroys an internal circuit device and greatly deteriorates the operation and yield of a chip, so that chips having high ESD immunity become competitive.
When a chip having a high voltage operation area is developed (for example, a BCD process), a latch-up free high voltage ESD device is typically developed in order to inhibit the operation of an ESD device in a high voltage operation area. Due to the high specifications of latch-up free and immunity level, the size of an ESD device is increased and this becomes a failure factor in minimizing a chip. The miniaturization of a high voltage ESD device is therefore a main factor in how competitive the ESD device is.
A commonly known ESD protection circuit technology in relation to the miniaturization of an ESD device includes an ESD protection device having a silicon controller rectifier (SCR) structure.
FIG. 1 shows a related art SCR structure, Referring to FIG. 1, a p+ diffusion area 51 of an SCR in an N well 50 is connected to an anode 30, and an n+ diffusion area 61 in a P well 60 is connected to a cathode 40 of an SCR. FIG. 3 shows an SCR characteristic curve according to a change of an anode voltage in such an ESD protection device, and its operation principle is as follows.
Referring again to FIG. 1, a voltage of the anode 30 drops in the N well 50) due to a pnp base current flowing through the N well 50, and when the voltage of the anode 30 becomes higher than that below an emitter, the emitter-base junction of a pnp transistor becomes a forward bias state and the pnp transistor is turned on. At this point, current flowing through the pnp transistor 10 flows into the P well 60, and due to this current, an npn transistor is turned on.
A current of an npn transistor flowing from the N well 50 to the cathode applies forward bias to the pnp transistor, and therefore, the SCR is triggered by the two turned on transistors (refer to A of FIG. 3). Through this, since there is no need to hold the bias in the pnp transistor, a voltage of the anode 30 is reduced to a minimum or near minimum value, and this is called holding voltage (refer to B of FIG. 3).
Then, the SCR performs a feedforward operation in order to effectively discharge an ESD current applied through the anode 30.
The ESD protection device further enhances current drivability conditions and latch-up free requirements, in which an ESD device does not operate in an operating voltage area, and also its size becomes smaller.